1. Field of the Invention
The invention relates to a method of plating for filling via holes in a multilayer circuit board.
2. Description of the Related Art
As a method of manufacturing a multilayer circuit board on which electronic devices, such as semiconductor chips, are mounted, a so-called build-up process is known.
A build-up process is described by referring to the drawings. In a build-up process, an insulation layer 12 is first formed on an underlying patterned wiring line 10 made up of copper or the like by the application or lamination of a material therefor (FIG. 13). A via hole 14 is then formed in the insulation layer 12 by laser machining or photolithography (FIG. 14). A copper plated layer 16 is subsequently formed so as to cover the inside of the via hole 14, where part of the patterned wiring line 10 is exposed at the bottom, and the top surface of the insulation layer 12, the copper plated layer 16 consisting of an electrolessly plated copper film 16a and an electroplated copper film 16b which are sequentially formed (FIG. 15). The copper plated layer 16 is then etched to provide an overlaying patterned wiring line 18 (FIG. 16). By the repetition of the above steps, a multilayer circuit board in which the lower wiring line 10 and the upper wiring line 18 are in electrical contact with each other through the plated films in the via hole 14, is produced.
When the insulation layer 12 is formed, the change in level on the surface of the formed insulation layer, which results from the underlying wiring line 10 having a top level higher than the surface of a substrate 8 on which the wiring line 10 is formed, can be cancelled by filling the inside of the via hole 14 with a conductor paste or insulating resin. However, such a process, which is also called a planarization process, increases the number of steps involved, and has a limited effect.
In the circumstances, a method of plating for via-filling in which the inside of a via hole is filled with copper plating has been proposed.
In the method of plating for via-filling, the inside of a via hole is designed to be filled with copper plating by, for example, contriving the agitation of a plating solution to thereby satisfactorily penetrate the inside of the via hole, or adding a plating promoting agent to thereby improve the throwing power of plating in the via hole.
However, filling via holes with copper plating has become difficult because patterned wiring lines have become more and more miniaturized and, accordingly, via holes are also miniaturized to have a large aspect ratio.
In particular, since a plating current tends to concentrate at a corner, there have been problems in that a large thickness of plating film is deposited at the edge of opening of the via hole to provide the via hole with a bottle neck, as illustrated in FIG. 17, and a plating solution is left in the via hole in the course of manufacturing a multilayer circuit board.
An object of the invention is to provide a method of plating for filling via holes in which even via holes having a small diameter and a large aspect ratio can be satisfactorily filled with copper plating.
The method of plating for filling via holes of the invention, in which each via hole formed in an insulation layer covering a substrate so as to expose, at its bottom, part of a conductor layer located on the substrate, is plated with copper to be filled with the plated metal, is characterized by comprising the steps of forming a copper film on the top surface of the insulation layer covering the substrate, and the side walls and bottoms of the respective via holes, immersing the substrate having the copper film formed in an aqueous solution containing a plating promoter to thereby deposit the plating promoter on the surface of the copper film, removing the plating promoter from the surface of the copper film located on the insulation layer and leaving the plating promoter on the side walls and bottoms of the respective via holes, and subsequently electroplating the substrate having the copper film formed with copper to thereby fill the via holes with the plated copper and simultaneously form a continuous copper film which eventually covers the via holes filled with the plated copper as well as the copper film previously formed on the insulation layer.
According to the above method, the plating promoter can be securely deposited within the via holes, and plating conditions in the via holes can be different from those on the top surface of the insulation layer. Also, a current for plating can be concentrated within the via holes, and even via holes having a large aspect ratio can be satisfactorily plated with copper.
As the plating promoter, a sulfur compound represented by the following general formula: 
wherein x denotes sodium, potassium, or hydrogen, R denotes hydrogen or an alkyl group, n is an integer of one or larger, and m is an integer of one or larger, can be used. Preferably, the alkyl group denoted by R has one to six carbon atoms. Preferably, n is selected from the integers of one to six, and m is also selected from the integers of one to six. The sulfur compound may be used in an aqueous solution containing a non-ionic surfactant for improving wettability of the solution, such as a polyethylene glycol or polypropylene glycol.
Examples of the plating promoters represented by formula (I) include sodium 3-mercapto-1-propanesulfonate and sodium 2-mercaptoethanesulfonate, and examples of the plating promoters represented by formula (II) includes disodium bis-(3-sulfopropyl)-disulfide.
The step of removal of the plating promoter from the surface of the copper film located on the insulation layer can be carried out by, for example, an etching process using an etching solution for copper, a cyanide electrolytic treatment using a cyanide electrolytic bath, a ultraviolet radiation treatment obliquely irradiating the surface of the copper film on the insulation layer with ultraviolet radiation, or a treatment of polishing the surface of the copper film on the top of the insulation layer.
It is also possible that the step of removal of the plating promoter on the surface of the copper film located on the insulation layer is omitted and, after the step of immersion of the substrate in a plating promoter-containing solution, a reverse electrolytic treatment is performed at an early stage of the step of electroplating with copper.
It is also possible that the step of removal of the plating promoter on the surface of the copper film located on the insulation layer is omitted and, after the step of immersion of the substrate in a plating promoter-containing solution, a pulse plating in which the direction of current applied is periodically reversed is used in the step of electroplating with copper.
It is preferred that, in the step of electroplating with copper, an electroplating solution free of a plating promoter is used.
In addition, an electroplating solution free of a plating promoter may be used in the step of electroplating with copper, carrying out the step of immersion of the substrate using, as the plating promoter, sodium 3-mercapto-1-propanesulfonate or sodium 2-mercaptoethanesulfonate, and omitting the step of removal of the plating promoter on the surface of the insulation layer.
It is also preferred that, prior to the step of immersion of the substrate in a plating promoter-containing solution, a strike plating of copper is provided on the surface of the copper film.